An integrated circuit (IC) is an electronic circuit formed using a semiconductor material, such as Silicon, as a substrate and by adding impurities to form solid-state semiconductor electronic devices (device, devices), such as transistors, diodes, capacitors, and resistors. Any reference to a “device” herein refers to a solid-state semiconductor electronic device unless expressly distinguished where used. Commonly known as a “chip” or a “package,” an integrated circuit is generally encased in hard plastic, forming a “package.” The components in modern day electronics generally appear to be rectangular black plastic packages with connector pins protruding from the plastic encasement. Often, many such packages are electrically coupled so that the chips therein form an electronic circuit to perform certain functions.
The software tools used for designing ICs produce, manipulate, or otherwise work with the circuit layout and circuit components on very small scales. Some of the components that such a tool may manipulate may only measure tens of nanometer across when formed in Silicon. The designs produced and manipulated using these software tools are complex, often including hundreds of thousands of such components interconnected to form an intended electronic circuitry.
A layout includes shapes that the designer selects and positions to achieve a design objective. The objective is to have the shape—the target shape—appear on the wafer as designed. However, the shapes may not appear exactly as designed when manufactured on the wafer through photolithography. For example, a rectangular shape with sharp corners may appear as a rectangular shape with rounded corners on the wafer.
Once a design layout, also referred to simply as a layout, has been finalized for an IC, the design is converted into a set of masks or reticles. A set of masks or reticles is one or more masks or reticles. During manufacture, a semiconductor wafer is exposed to light or radiation through a mask to form microscopic components of the IC. This process is known as photolithography.
A manufacturing mask is a mask usable for successfully manufacturing or printing the contents of the mask onto wafer. During the photolithographic printing process, radiation is focused through the mask and at certain desired intensity of the radiation. This intensity of the radiation is commonly referred to as “dose”. The focus and the dosing of the radiation has to be precisely controlled to achieve the desired shape and electrical characteristics on the wafer.
A device generally uses several layers of different materials to implement the device properties and function. A layer of material can be conductive, semi-conductive, insulating, resistive, capacitive, or have any number of other properties. Different layers of materials have to be formed using different methods, given the nature of the material, the shape, size or placement of the material, other materials adjacent to the material, and many other considerations.
The software tools used for designing ICs produce, manipulate, or otherwise work with the circuit layout and circuit components on very small scales. Some of the components that such a tool may manipulate may only measure a few nanometers across when formed in Silicon. The designs produced and manipulated using these software tools are complex, often including hundreds of thousands of such components interconnected to form an intended electronic circuitry.
A Field Effect Transistor (FET) is a semiconductor device that controls the electrical conductivity between a source of electric current (source) and a destination of the electrical current (drain). The FET uses a semiconductor structure called a “gate” to create an electric field, which controls the shape and consequently the electrical conductivity of a channel between the source and the drain. The channel is a charge carrier pathway constructed using a semiconductor material.
Within the scope of the illustrative embodiments, the structures in a pair of structures are parallel to one another if at least one surface of each of the structures in the pair faces the other structure, and such surfaces are substantially parallel to one another in at least one direction. The parallel surfaces of such structures in the pair need not be exactly parallel, but may run along each other without touching each other, and separated by some distance. Within the scope of the illustrative embodiments, adjacent structures that satisfy these properties can be regarded as parallel structures unless expressly distinguished where used.
Gates of a finFET are a non-limiting example of parallel structures used to describe the various embodiments herein. These examples of parallel gates are not intended to be limiting. From this disclosure, those of ordinary skill in the art will be able to conceive many other parallelly formed structures that suffer from a similar problem of bending, and can benefit from the techniques described herein to prevent or reduce such bending, and the such other parallel structures are contemplated within the scope of the illustrative embodiments.
The illustrative embodiments recognize that forming structures that extend parallel to one another in a direction has certain inherent problems. For example, in some cases, forming such structures results in some structures being of shorter lengths than the desired length.
As another example, the proximity of the parallel structures to one another—which can be of the order of a few nanometers (nm), e.g., 4-10 nm—causes capillary action and other phenomena to exert forces on the parallel structures that cause one of the parallel structures to bend towards the other, or both parallel structures to bend towards each other. This bending causes the structures to no longer be parallel, a gap or another structure intervening the parallel structures to become tapered at the distal end of the parallel structures.
The bending of the parallel structures, the tapering of the intervening space or structure, or both, can result in undesirable electrical properties of the parallel structures, the space, the intervening structure, or some combination thereof. Therefore, the parallel structures should be fabricated in such a manner that the bending tendencies in parallel structures are discouraged, reduced, or prevented. Therefore, a method for reducing bending in parallel structures in semiconductor fabrication would be desirable.